Minimization and generation of next-state expressions for asynchronous sequential circuits

One step in the synthesis procedure for realizing an asynchronous sequential circuit that is operating in fundamental mode is to obtain an internal-state assignment that will realize the operations of the circuit. Often the procedures that are used in accomplishing the above task generate several satisfactory assignments. The first part of this paper presents a method that will enable one to predict which of the internal-state assignments will yield a simpler set of next-state expressions. A second topic treated in this paper is one of presenting a method to generate the next-state expressions for an asynchronous sequential circuit directly from the internal-state assignment. An algorithm is presented for generating the next-state expressions without construction of the transition table --Abstract, page ii

State assignments for non-normal asynchronous sequential circuits

There is a lack of procedures that can be used to find good internal state assignments for asynchronous sequential circuits operating in the non-normal mode. Presented here, are two generalized state assignments, which are functions only of the number of rows in a flow table. The suggested bounds for the generalized state assignments are m + [log₂m] and m + [m/2] internal state variables for a 2m-row flow table, where [ ] means next lowest integer . Both generalized state assignments produce group (linear) codes. The algorithms for generating these internal state assignments are easy and straight-forward to implement. It is shown that each of these state assignments satisfactorily encode certain classes of flow tables. Even though a general proof has not been found to show that these assignments were standard, worst-case situations have been constructed, and it has never been necessary to increase the suggested bounds. An internal state assignment procedure for obtaining non-standard or non-generalized state assignments is also presented. The internal state assignments, using the proposed method, are obtained in a systematic manner; and generally require fewer internal state variables than other procedures presently available --Abstract, page ii

NASA SERC 1990 Symposium on VLSI Design

This document contains papers presented at the first annual NASA Symposium on VLSI Design. NASA's involvement in this event demonstrates a need for research and development in high performance computing. High performance computing addresses problems faced by the scientific and industrial communities. High performance computing is needed in: (1) real-time manipulation of large data sets; (2) advanced systems control of spacecraft; (3) digital data transmission, error correction, and image compression; and (4) expert system control of spacecraft. Clearly, a valuable technology in meeting these needs is Very Large Scale Integration (VLSI). This conference addresses the following issues in VLSI design: (1) system architectures; (2) electronics; (3) algorithms; and (4) CAD tools

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers

Pass-transistor very large scale integration

Logic elements are provided that permit reductions in layout size and avoidance of hazards. Such logic elements may be included in libraries of logic cells. A logical function to be implemented by the logic element is decomposed about logical variables to identify factors corresponding to combinations of the logical variables and their complements. A pass transistor network is provided for implementing the pass network function in accordance with this decomposition. The pass transistor network includes ordered arrangements of pass transistors that correspond to the combinations of variables and complements resulting from the logical decomposition. The logic elements may act as selection circuits and be integrated with memory and buffer elements

A State Assignment Procedure For Asynchronous Sequential Circuits

This paper presents a new procedure for constructing nonuniversal shared-row internal state assignments for asynchronous sequential circuits. The method consists basically of establishing an initial code with the minimum number of variables required to dis. © 1971, IEEE. All rights reserved

State Assignment Selection In Asynchronous Sequential Circuits

Methods already exist for the construction of critical race-free assignments for asynchronous sequential circuits. Some of these methods permit the construction of many assignments for the same flow table. The algorithm presented here consists of two easy to apply tests which select that critical race-free assignment most likely to produce a set of simple next-state equations. The algorithm has been programmed. Copyright © 1970 by The Institute of Electrical and Electronics Engineers, Inc

Maximum-Distance Linear Codes

Described here is a linear code that has a maximum distance between codewords of k for a code of order 2k. Since the minimum-maximum distance is k for a code of order 2k, a class of minimum-maximum distance codes results. For an (n,k) linear code, k ≤ n ≤ k + k∣2 for k even and k ≤ n ≤ k + (k - 1)/2 for k odd. Maximum-distance codes are found useful in encoding the states of sequential circuits. © 1971, IEEE. All rights reserved

Piping Load Effect On Shaft Vibration In A Multi-Stage Barrel Type Boiler Feed Pump

Case Stud